The present disclosure relates generally to integrated circuits (ICs), which may include programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs). More particularly, the present disclosure relates to overcoming retiming limitations due to initial conditions conflicts in circuit designs for an integrated circuit.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits (ICs) take a variety of forms. For instance, programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs) are ICs that may be highly flexible devices. FPGAs include logic that may be programmed after manufacturing to provide functionality that the FPGA may be designed to support. Thus, FPGAs contain programmable logic, or combinational logic blocks, that may perform a variety of functions on the FPGAs, according to a circuit design of a user. In a programmable logic circuit design, groups of combinational logic elements may be separated by registers. At each clock cycle, a data signal may exit one register, be processed through a first group of combinational logic elements, and enter another register to wait for the next clock cycle to begin. At the next clock cycle, the data signal may continue through a second group of combinational logic elements into a third register, and so forth. Thus, the way that the registers separate different groups of combinational logic elements may have a substantial impact on the maximum achievable clock signal frequency by which the data signal may pass through the programmable logic circuit design. The maximum clock signal frequency may depend on how quickly the data signal can pass through a group of combinational logic elements between any two registers of the circuit design. One technique to improve the performance of the circuit design is through register retiming, which involves adjusting the placement of the registers back and forth across different groups of combinational logic to improve the maximum achievable clock signal frequency.
However, the benefits of retiming are often limited due to the use of certain constructs in circuit designs that inadvertently inhibit retiming. Such restrictions might include user directives intended for other purposes but that also limit retiming; the use of certain hardware features, such as asynchronous clears, that might be incompatible with retiming on some architectures; or even simply the lack of sufficient available registers for retiming. Even if some computer aided design (CAD) tools were able to remove these restrictions or add registers to demonstrate the performance potential of retiming with changes to the user's circuit design, this may involve computing new power-up states for retimed registers to ensure functional equivalence with the initial circuit design.
Some CAD tools that perform retiming preserve the functionality of the circuit (before and after retiming) over the range of inputs that will occur during operation of the initial circuit design. For this reason, the retiming tools generally try to fully preserve the power up behavior of an initial circuit design when performing retiming. This can be done by computing initial power up conditions for any individually retimed registers. In practice, it is not always possible to compute new register initial conditions that guarantee identical circuit performance. For example, there may be one or more conflicts with the initial conditions. This limitation will result in rejected retiming moves, and an overall reduction in the benefits of automatic retiming. Further, the user may be unaware of which registers were involved in the one or more conflicts and/or an expected performance improvement that could be achieved if the one or more conflicts were addressed.